1. Field of the Invention
The present invention relates to field programmable logic arrays (FPLAs). More specifically, the present invention relates to circuits for programming and verifying field programmable logic arrays.
While the present invention is described herein with reference to illustrative embodiments for particular applications, it should be understood that the invention is not limited thereto. Those having ordinary skill in the art and access to the teachings provided herein will recognize additional modifications, applications, and embodiments within the scope thereof and additional fields in which the present invention would be of significant utility.
2. Description of the Related Art
Programmable logic arrays (PLAs) provide `glue logic` for printed circuit boards. Glue logic is the logic required to interface integrated circuits within a board and/or several boards and generally includes a plurality of AND gates, OR gates and input/output I/O buffers. PLAs consume less space and therefore generally provide glue logic in a less costly manner than individual AND gates, OR gates and I/O buffers.
PLAs also offer the advantage of user configurability or programmability over discrete or individual gates. That is, PLAs generally include an array of `AND` gates, an array of `OR` gates, and some provision for interconnecting the outputs of selected AND gates to the inputs of selected OR gates. PLAs allow a wide variety of logic functions to be implemented through the combination, via the OR gates, of the product terms, provided by the AND gates. Further, the configuration of the field programmable logic arrays FPLAs (and programmable array logic circuits such as the PAL devices manufactured by Advanced Micro Devices of Sunnyvale, Calif.) may be quickly, easily and relatively inexpensively reprogrammed by the user to implement other functions. See U.S. Pat. No. 4,124,899.
Programming of the array is typically performed in a fixture which provides proper programming voltage levels to the integrated cell to allow the cells to be programmed (e.g. electrically erasable or EECELLS) providing the AND functions. Nonetheless, the programming signals must be maintained at appropriate levels for a minimum period of time. After each cell is programmed, the entire array must be verified. This is time consuming given the large number of cells in current arrays. In addition, there are other shortcomings associated with the current approaches for programming and verifying the array of an FPLA.
One approach involves the use of a binary addressing scheme by which the array cells are addressed and programmed as if the array were a memory. Unfortunately, this approach is difficult to implement in that it requires the routing of many additional control signals throughout the chip, since the chip is not organized to perform as a memory in the normal operating mode.
A second approach involves the use of a shift register. With this approach, programming data is serially shifted into the loaded register, loaded in parallel into the array, back into the shift register and serially shifted out of the shift register for verification. That is, during verification, the sense amplifiers data is loaded into the shift register. (Sense amplifiers detect state changes in the array and output product terms therefrom.) This requires the shift registers to be located close to the sense amplifiers in a crowded area on the die. This approach is slow and imposes awkward chip layout requirements on the designer.
Thus, there is a need in the art to reduce the time required to program and verify field programmable logic arrays. In addition, as the logical components must be integrated with programming components, on a chip of limited die area, there is a further need in the art to simplify the layout and die space requirements of FPLAs.